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Session Track: General
Light Lunch Buffet
  • Speaker:  
Time: Monday, May 15, 12:00 - 13:30, Room: Conference Area
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Session Description: Light Lunch Buffet

Session Track: Academic
[AC01] Updated Cadence® 2017 Portfolio Available for European Academics via Europractice (Europractice)
  • Speaker: Emily van der Heijden, Science and Technology Facilities Council 
Time: Monday, May 15, 13:30 - 14:00, Room: Pilsensee
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Session Description: Based at the Rutherford Appleton Laboratory, in Oxfordshire, UK, The STFC Microelectronics Support Centre runs the Europractice Software Service, and has partnered with Cadence for more than 25 years to provide Cadence EDA tools to academia in the EMEA region. This session will provide information on the full range of services offered by the STFC Microelectronics Support Centre through the Europractice project. This includes IC Design Methodology training on Cadence tools and our Europractice partners' provision of Design Kits and MPW services from a wide range of foundries, in addition to provision and full technical support of Cadence licenses for European academia.

Emily van der Heijden Bio: Emily van der Heijden is a Principal Engineer and Mixed Signal IC Methodology Lead in the Science and Technology Facilities Council's Microelectronics Support Centre. Based at the Rutherford Appleton Laboratory, in Oxfordshire, UK, The STFC Microelectronics Support Centre runs the Europractice Software Service, and has partnered with Cadence for more than 25 years to provide Cadence EDA tools to academia in the EMEA region. Emily is responsible for managing the full range of Cadence tools within the Europractice portfolio.
Session Track: Automotive and IP Solutions
[ASIP01] Using a Single Core for 3GPP NB-IoT and Your Desired IoT Application - CommSolid's CSN130 is the Solution. (CommSolid)
  • Speaker: Matthias Weiss, Managing Director, CommSolid 
Time: Monday, May 15, 13:30 - 14:00, Room: Schliersee
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Session Description: Tailored for Ultra-Low Power Cellular Communication Smart devices need to operate everywhere. CSN130 uses the existing cellular network infrastructure and site density. Employing the 3GPP NB-IoT standard, it provides an improved link budget of 20dB compared to LTE, WCDMA or GPRS. In turn, devices at any place in the world can be reached – also in signal challenging areas like basements, tunnels and remote rural areas. CSN130 is size optimized to fit in any kind of device – no matter how small it is. On top, it supports enhanced power saving procedures for long and efficient sleep times. This enables cellular communication with ultra-low power consumption securing long battery life and reducing maintenance. Flexible architecture allows for customization und evolution The CSN130 modem IP is designed for embedded customer solutions, starting from slim modems through simple SoCs with integrated RF and sensor interfaces to complex SoCs with application processors and multi-mode wireless support. It depicts a complete pre-certified NarrowBand-IoT modem consisting of hardware description and software stack. CSN130 comes along with all interfaces and documentation needed for an easy and seamless integration, CSN130 is verified on a reference platform and will be delivered with predefined test cases. The CSN130 heartbeat is provided by the Cadence Fusion F1 DSP core, a powerful solution enabling NB-IoT modem operation and execution of IoT applications in parallel. In combination with the flexible architecture it offers sufficient headroom for customization and also for evolution towards 3GPP Release 14 or future requirements. “CSN130 has been developed in record time from the ground-up with focus on robustness and optimized size and power figures”, states Lars Melzer, Managing Director at CommSolid. “The selection of the Cadence Fusion F1 DSP core allowed for usage of just one DSP for the complete solution while providing adequate headroom for additional customer applications as for instance voice, temperature or humidity recognition.”

Matthias Weiss Bio:
Session Track: Custom
[CUS01] Schematic Driven Block Isolation: No More Verification Gaps (NXP Semiconductors)
  • Speaker: Sergey Yevstigneev, PDK Manager, NXP Semiconductors
    Vladimir Slezkin, manager, NXP Semiconductors
    Alexey Efishin 
Time: Monday, May 15, 13:30 - 14:00, Room: Ammersee I
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Session Description: Analog-mixed signal designers are always worry about block isolation from noise or hot carrier injection. Since guard rings result in additional parasitics, leakages and additional proximity effects everybody would like to estimate the impact on schematic side first and then be sure that layout contains exactly the same isolation topology. These requirements lead to schematic driven layout isolation technique with guaranteed verification method that a particular group of devices is seating inside of a particular isolation ring. This article describes PDK nested block isolation methodology with new physical verification engine of isolated content. In comparison with traditional connectivity based LVS methods the new one looks for the device isolation fact itself. With that we filled gaps of verification of dielectric type of isolation in general and also the particular case where global and isolated substrates are shorted together.

Sergey Yevstigneev Bio: Sergey Yevstigneev received Master degree in Moscow Institute of Electronic Engineering in 1996. Philosophy degree in solid-state physics was received in the same university in 1999. From 1999 he is working in Motorola/Freescale and now NXP Process Design Kit (PDK) department. Starting from 2004 Sergey is managing Moscow PDK team.
Vladimir Slezkin Bio: Slezkin Vladimir, 1992-1997, Moscow Institute of Electronic Technology (MIET), engineer; 1997-2001, Moscow Institute of Electronic Technology, post-graduate education, Ph.D. in EDA (Electronic Design Automation) 2001-2008, “Microstyle”, PDK development, engineer 2008-now “Freescale semiconductor” then NXP, PDK development, engineer, project leader. 20+ Years’ experience in EDA
Alexey Efishin Bio:
Session Track: Digital Implementation and Signoff
[DSG01] 25 Best HLS Coding Practises
  • Speaker: Andries Hekstra, Senior scientist, NXP Semiconductors 
Time: Monday, May 15, 13:30 - 14:00, Room: Ammersee II
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Session Description: Few IC designer would contest that the ever larger number of transistors per chip makes it logical to do digital designs at a higher layer of abstraction. This is known as High Level Synthesis (HLS). However, the successful adoption of HLS requires the familiarization with a programming language and a compiler that may take an amount of time not readily available in many companies, anno 2017. Since 2008, we have very successfully taped out two error correcting decoder IPs in HLS. We also used HLS as a side track in algorithmic research projects (wideband ADC linearization, FM radio), in which we lacked success with the algorithms we devised, not with the use of HLS. In this contribution, we focus on practical aspects users face during adoption of HLS, also with design of larger systems, and enumerate ca. 25 very concrete coding practices that are intended to make other HLS users more effective. With the large leverage of HLS compilation for the IP one can cover in a certain time, robustness of the HLS tool is paramount, for which Cadence Stratus has our preference.

Andries Hekstra Bio: In 1985, Andries graduated cum laude from Eindhoven Univ. of Techn. in Electr. Eng., specializing in information theory. He started as a young graduate trainee at European Space Agency, Darmstadt, Germany, and moved on to become a Ph. D. candidate at Cornell University for four years. He joined the research dept. of Dutch telecom operator KPN in 1990, working on video coding, later human scale video and audio quality assessment with computer algorithms, where he obtained a Ph.D. from the same university. In 2001 he moved to Philips Research, working initially on 2-dimensional optical recording and error correction coding for successors of Blu-ray disc (cooperation with Sony Research). When NXP divested from Philips in 2006, he transferred to NXP Research' digital baseband group. After a mobile reception study for DVB-T, in 2008 he became enthusiastic about high level synthesis, focussing on accelerator IPs.
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